설계독학

@verilog

Est. 2011·South Korea·Korean·~0.2 vids/wk

New on TrySpansa

설계독학 is a Tech and Education YouTube creator with 7.3K subscribers and 450K total views. The channel covers semiconductor design, korean language tech education, verilog hdl, fpga programming, hardware design. Active for 14 years, the channel publishes about 12 videos per year. Videos average 2.6K views each. Based in South Korea, the channel's primary language is Korean. YouTube channels with 1K–10K sub channels typically charge between $50 and $500 per sponsored video. Book a sponsorship directly on TrySpansa.

7,340Subscribers

172Total Videos

450,170Total Views

Source: YouTube Data API

Views / Video284K

Impressions1.2M

Age Demographics

13-17

18-24

35%

25-34

28%

35-44

16%

45-54

55-64

65+

Gender Split

Male 62%Female 36%Other 2%

Core: Male 18-24

Top Countries

🇺🇸United States

28%

🇬🇧United Kingdom

18%

🇧🇷Brazil

12%

🇮🇳India

🇩🇪Germany

Traffic Sources

34%

Suggested

24%

External

14%

Browse

12%

Content Performance

128KAvg Views

4.2%CTR

+1.2KNet Subs

3:42Watch Time

Subscriber Growth

6 mo agoToday

Device Split

Desktop

48%

Mobile

34%

Tablet

11%

Watch Time

8:42Avg Duration

42%Retention

2.1MHours

6.8Views/Visit

Content Type

Long-form

55%

Shorts

28%

Live

12%

Members

Free · 10 seconds · No credit cardSee 설계독학’s audience data

Niches

TechEducation

About

한국인을 위한, 반도체 설계를 학습할 수 있는 설계독학 채널 입니다! 세상에 없던, 반도체 설계 현업자에게 도움이되는 실무 강의를 현직자가 직접 만듭니다. Verilog HDL, FPGA, ASIC, AI, Video, HLS 등 시스템 반도체 설계를 위주로 진행합니다. 많이 놀러와 주세요!

Recent Videos

AI 시대에도 필요한 코딩 테스트 완벽대비 | (실전 코테 끝판왕: 고난도 문제로 완성하는 이직 프리패스) #ai #rtl #programming #verilog

AI 시대에 준비해야 하는 Verilog Master Season2 강의소개 (실전 코테 끝판왕: 고난도 문제로 완성하는 이직 프리패스)

[Verilog 마스터 S2][L2-P12] 우선순위 데이터 컨트롤 : 다중 요청을 처리하는 Arbitration(중재) 로직 설계

[Verilog 마스터 S2][L2-P11] PWM (Pulse Width Modulation) : 하드웨어 타이머와 신호 제어의 정석

[Verilog 마스터 S2][L2-P10] CDC (Clock Domain Crossing) : 👑 면접 1순위! 비동기 클락 도메인 완벽 처리

[Verilog 마스터 S2][L2-P09] 파이프라인 (Pipeline) : 동작 주파수(fmax)를 끌어올리는 하드웨어의 마법

[Verilog 마스터 S2][L2-P08] 동기식 SRAM : 메모리 인터페이스 설계와 타이밍 이해

[Verilog 마스터 S2][L2-P07] FSM 나눗셈 : 순차 회로를 활용한 산술 연산 구현

Channel data updated June 2026

youtube.com/@verilog

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Channel Videos설계독학

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YouTube Data API: 7,340 subscribers

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Using Tech benchmark: 3.6% (Electronics & Appliances) · Skailama 2026

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Using Tech benchmark: 1.6× /year · Beans 2021 freq × Bluecore/MobiLoud RPR

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Methodology & sourcesNot sourced from YouTube

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Topicsclassified by TrySpansa

semiconductor design korean language tech education verilog hdl fpga programming hardware design digital design asic design video processing embedded systems technical tutorials coding education engineering career guidance fpga development boards

Resources

The Brief Isn't Dead. Unstructured Briefs Are. →NY Synthetic Performer Law: AI Clauses Your Deal Needs →Creator Payment Rails 2026: 5 Compared (Plus 1 Imposter) →

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설계독학

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